1. Field of the Invention
The present disclosure relates to alignment monitoring structures and methods for semiconductor devices and, more particularly, to alignment monitoring structures and methods for monitoring the alignment between target gate conductors and the corresponding target contacts in a semiconductor device.
2. Description of the Related Art
In semiconductor devices of the state-of-the-art and, in particular in CMOS products, it is crucial to have a good control of the alignment of the contact patterning to the gate patterns in order to prevent unintended contact-to-gate shorts. Typically, the alignment is checked by optical means at a few positions per exposure field only, so that systematic contributions to the alignment error inherent to photomask production are not avoided. Local information on alignment quality is not available. The size required for optical alignment marks prevents their placement within the chip, whose size is typically reduced.
In view of the above-described situation, it is, therefore, desirable to provide an alignment monitoring structure and a method for monitoring the alignment between target gate conductors and the corresponding target contacts such that the above-described issues and problems are at least reduced, if not avoided.